Wire routing congestion is a primary limitation on the design of a network-on-chip (NoC). Chips can have hundreds of semiconductor intellectual property (IP) cores connected through the network. The locations of IP-NoC interface sockets are generally fixed or constrained to certain regions. With a high degree of data transfer connectivity between IPs, a tremendous number of wires must be routed within the hallways between blockages in the floorplan of a chip. Routing such large numbers of wires requires a lot of manual work in the back end of the chip design process. If routing cannot be achieved successfully then changes are necessitated at the front end, and that adds significant delay to completing the chip design.
Routing is a process that, conventionally, is done in the back end part of a chip design project without any particular planning in the front end part. Logic design, and particularly higher-level design such as NoC topologies used to generate logic, creates problems for the back-end design engineers to solve in every project. This unpredictably delays the completion of chip designs headed for manufacturing.
The place & route problem can be reduced by dividing the NoC into a set of switches connected by links. Each switch aggregates the traffic of one or more logically upstream ports and one or more logically downstream ports. Links between switches thereby carry the network traffic of multiple IPs on a single set of wires. The full data transfer connectivity of the NoC is still available, just in a way that shares wires in order to reduce routing congestion. However, an optimal topology of switches and links is far from obvious.
Another problem is closing timing. Throughout the history of generations of chip design technologies, the sizes of chips have remained fairly constant, the clock cycle periods have decreased, and the propagation delay of signals on wires has increased. That means that it takes more than one and in some cases many cycles for information to propagate from one IP to another.
To accommodate this reality, pipeline stages are used within switches and on links in NoC designs. Pipeline stages within switches are expensive because they usually must be replicated for multiple ports within the switch. Since the length of links can vary, the number of pipeline stages required on links between switches to close timing can be from zero to many. The topology of switches and links should ideally be designed in order to minimize the number of pipeline stages. How many pipeline stages to place, and how to design the topology with them in mind, is far from obvious. Therefore, what is needed is a method and system for designing a near-optimal NoC topology of localized switches connected by pipelined links.